A solution manual to Computer Architecture: A Quantitative by John L. Hennessy & David Patterson

By John L. Hennessy & David Patterson

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This can reduce the efficiency of execution, which has implications for power consumed and for total performance in a multithreaded environment. Sometimes the off-path instructions can initiate useful memory subsystem operations early, resulting in a small performance improvement. k. A static data dependence graph is constructed with nodes representing static instructions and arcs representing control flows and data dependences. 26 shows a simplified static data dependence graph for the hash table code.

The minimal transfer time divided by the rotational latency determines the x-axis value of point 3, as it reflects the number of sectors traversed in that time. The slope of the lines L1 . . L4 is determined by dividing the rotational time by the number of sectors per track; L2 is the base line and essentially goes through the y-axis at x = 0, L3 is just a head switch time above L2, and L4 a cylinder switch time above L2. The most difficult aspect of drawing the graph, then, is determining exactly where each point goes.

120: (DM, {P1}, 00 20) Memory is not updated on a write to a block that is M in another cache. 17 a. P0: write 100 <-- 80 No messages, hits in P0’s cache b. P0: write 108 <-- 88 Send invalidate to P15 c. P0: write 118 <-- 90 Send invalidate to P1 d. 32. 31 Cache states. 32 Directory states. 19 The Exclusive state (E) combines properties of Modified (M) and Shared (S). The E state allows silent upgrades to M, allowing the processor to write the block without communicating this fact to memory. It also allows silent downgrades to I, allowing the processor to discard its copy with notifying memory.

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